Bookmark this page

New
mpn: TS256MLQ72V8U

2GB 800MHZ DDR2 ECC DR X8 CL6 WORKSTATION/SERVER DRAM

Highlights

  • RoHS compliant products
  • JEDEC standard 1.8V ± 0.1V power supply
  • Programmable sequential / Interleave burst mode
  • Bi-directional differential data-strobe (Single-ended data-strobe is an optional feature)
  • Off-chip driver (OCD) impedance adjustment
  • MRS cycle with address key programs
  • On die termination
  • Serial presence detect with EEPROM

Marketing description

The TS256MLQ72V8U is a 256M x 72bits DDR2-800 unbuffered DIMM. The TS256MLQ72V8U consists of 18 pcs 128Mx8bits DDR2 SDRAMs in 68 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin printed circuit board. The TS256MLQ72V8U is a dual in-line memory module and is intended for mounting into 240-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Capacity

Upgrade Type

Type

Technology

Form Factor

Standard Warranty


TS256MLQ72V8U

2GB 800MHZ DDR2 ECC DR X8 CL6 WORKSTATION/SERVER DRAM

Highlights

  • RoHS compliant products
  • JEDEC standard 1.8V ± 0.1V power supply
  • Programmable sequential / Interleave burst mode
  • Bi-directional differential data-strobe (Single-ended data-strobe is an optional feature)
  • Off-chip driver (OCD) impedance adjustment
  • MRS cycle with address key programs
  • On die termination
  • Serial presence detect with EEPROM

Marketing description

The TS256MLQ72V8U is a 256M x 72bits DDR2-800 unbuffered DIMM. The TS256MLQ72V8U consists of 18 pcs 128Mx8bits DDR2 SDRAMs in 68 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin printed circuit board. The TS256MLQ72V8U is a dual in-line memory module and is intended for mounting into 240-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Technical Specifications

Capacity
Upgrade Type
Type
Technology
Form Factor
Module Height (inch)
Speed
Latency Timings
Data Integrity Check
Features
Module Configuration
Chips Organization
Voltage
Compatible Slots
Compliant Standards
Service & Support
Designed For
Product Description
Product Type
Memory Type
Manufacturer Warranty
manufacturer
last_sync

Standard Warranty